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dev_sg features a 6 channel differential ADC with integrated programmable gain amplifier (PGA), with the following parameters:

Analog sampling rate 2kHz
Number differential channels 6
Number of bits 24
ADC reference voltage 1.2V

ADC operation

ADC values are sampled, and amplified via hardware PGA. The values are then normalised to the range [-1, 1], then an optional low pass filter may be applied. The ADC values are then passed through the transform subsystem, before being output as JCS signals.

ADC user configuration

Channel PGA gain

Select the ADC gain for channel X by writing an enum to adc_channel_X_gain (where X is 0, 1, 2, 3, 4 or 5):

Gain parameter Description
ads131m06_gain_1 Gain: 1x
(Default value)
ads131m06_gain_2 Gain: 2x
ads131m06_gain_4 Gain: 4x
ads131m06_gain_8 Gain: 8x
ads131m06_gain_16 Gain: 16x
ads131m06_gain_32 Gain: 32x
ads131m06_gain_64 Gain: 64x
ads131m06_gain_128 Gain: 128x


When operating with channel gain settings at: 8, 16, 32, 64 or 128, the ADC input voltages must not exceed 1.5V.

Channel mux

Configure the ADC input multiplexer by writing an enum to adc_channel_X_mux (where X is 0, 1, 2, 3, 4 or 5):

Mux parameter Description
ads131m06_mux_ainp_ainn \(Ain_p\) and \(Ain_n\) are connected to the external pins
(Default value)
ads131m06_mux_shorted \(Ain_p\) and \(Ain_n\) are shorted to ground
ads131m06_mux_pos_dc_test Positive DC test signal of around \({2 \over 15} \times v_{ref} = {2 \over 15} \times 1.2V = 160mV\)
ads131m06_mux_neg_dc_test Negative DC test signal of around \({2 \over 15} \times v_{ref} = {2 \over 15} \times 1.2V = 160mV\)


The DC test signal scales with the selected gain. For example, gain = 1, test voltage = 160mV, gain = 2, test voltage = 80mV


The ADC channel and mux configuration values are only sampled at startup. Any changes to the mux or channel configuration while JCS is running will have no effect. To re-configure the mux or channel values, a jcs_host API call to stop, then start is required.

ADC filter

The normalised ADC values may be passed through a first order low pass filter (one per channel), before being passed to the transform subsystem. The filters are either enabled for all channels, or disabled for all channels.

Enable or disable the ADC filter by writing an enum to adc_filter:

Filter mode Description
adc_filter_disabled ADC filters disabled for all channels.
(Default value)
adc_filter_enabled ADC filters enabled for all channels.

Configure the ADC filter with:

Commands Type Required Description
adc_filter_fc_hz float32 Optional Filter cutoff frequency.
Default: 1kHz